This invention relates to direct memory access (DMA) transfers between peripheral devices and a memory via a DMA controller acting as a bus master located on a processor local bus (PLB).
In the recent past, significant advances in silicon densities have permitted the integration of many functions onto a single silicon chip which includes the processor. The increase in density has allowed the integration of some peripheral functions which were formerly implemented at the card level over a system level bus. Some of the functions being integrated on the chip include audio, video and graphics. These functions have increased bandwidth requirements and require efficient utilization of the on-chip bus used to transfer data between a memory and the peripherals.
In most applications several bus masters, such as DMA controllers, share an on-chip processor local bus (PLB) under control of a bus arbiter. It is essential that the bus masters relinquish the bus as soon as they no longer require it in order to improve bandwidth utilization. However, it is also more efficient to retain control of the bus when a peripheral requires back-to-back data transfers. The two requirements present a conflict.
Once a DMA Acknowledge (DMAA) signal is asserted by the DMA controller to signal a data transfer, the peripheral will use the DMA Acknowledge (DMAA) to de-assert its request if it requires no more transfers. Due to delays, this event takes place very late in the clock cycle. Therefore, the de-assertion of a request must be single latched by the DMA before it can be sampled. PLB bus master requests must start at the beginning of a clock cycle (driven off the output of a latch). For a single clock cycle DMA Acknowledge, the earliest the DMA can sample the peripheral request is the clock after the DMAA. Unfortunately, the DMA cannot instantaneously turn its bus master request on based on the sampling of the peripheral request. Therefore, the DMA must wait for one clock and then assert its PLB bus master request if the peripheral has its request active for another transfer cycle. This results in a lost or "dead" clock cycle between back-to-back DMA peripheral transfers.